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Home/ Questions/Q 877757
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Editorial Team
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Editorial Team
Asked: May 15, 20262026-05-15T11:39:45+00:00 2026-05-15T11:39:45+00:00

I’m using Make and I have a makefile which sets a variable with a

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I’m using Make and I have a makefile which sets a variable with a value that I need to override from a parent makefile. I’ve tried setting the variable in the parent makefile and using export to pass it to the submake but the variable is not using the passed down value, instead it is using the value explicitly set in the sub-Makefile.

I know that variables specified on the command line override any ordinary assignments in the makefile (unless override is used) but is there a way to achieve this for submakes without having to specify it on the command line for each invocation of the submake (because there are quite a few and I like to stay DRY)?

UPDATE

I should have mentioned that I can’t modify the submake file because it’s from an external repository that we track and I don’t have the authority to modify it so I need to work at the parent makefile level to influence the submake.

EXAMPLE

Here’s a representative target in the parent makefile that’s calling the submake:

$.PHONY (external_lib)
$(external_lib): 
    $(MAKE) -C $(source_dir)/project/component $(PROJECTVARS) make_a
    $(MAKE) -C $(source_dir)/project/component $(PROJECTVARS) make_b
    $(MAKE) -C $(source_dir)/project/component $(PROJECTVARS) make_c
    $(MAKE) -C $(source_dir)/project/component $(PROJECTVARS) make_d
    $(MAKE) -C $(source_dir)/project/component $(PROJECTVARS) make_e
    $(MAKE) -C $(source_dir)/project/component $(PROJECTVARS) make_f
    $(MAKE) -C $(source_dir)/project/component $(PROJECTVARS) make_g
    $(MAKE) -C $(source_dir)/project/component $(PROJECTVARS) make_h
    $(MAKE) -C $(source_dir)/project/component $(PROJECTVARS) make_i
    $(MAKE) -C $(source_dir)/project/component $(PROJECTVARS) library
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1 Answer

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  1. Editorial Team
    Editorial Team
    2026-05-15T11:39:45+00:00Added an answer on May 15, 2026 at 11:39 am

    (You appear to be using something other than GNUMake, which is the only Make I know, so take this with a grain of salt.)

    First you can make your Makefile tidier by making the components separate targets:

    COMPONENTS =  make_a make_b make_c make_d make_e make_f make_g make_h make_i \
            library
    
    .PHONY: external_lib $(COMPONENTS)
    $(external_lib): $(COMPONENTS)
    
    $(COMPONENTS):
        @$(MAKE) -s -C $(source_dir)/project/component $(PROJECTVARS) $@
    

    (If you’re worried about name collisions, there are simple ways to deal with that.)

    Now if you want to override a variable called, say, VAR, you can do it all in one place:

    COMPONENTS =  make_a make_b make_c make_d make_e make_f make_g make_h make_i \
            library
    
    .PHONY: external_lib $(COMPONENTS)
    $(external_lib): $(COMPONENTS)
    
    $(COMPONENTS):
        @$(MAKE) -s -C $(source_dir)/project/component $(PROJECTVARS) VAR=$(VAR) $@
    

    This assumes that you want to override the same variable for all components, which is how I read the question. If you want to override a different variable for some targets, that’s easy:

    COMPONENTS =  make_a make_b make_c make_d make_e make_f make_g make_h make_i \
            library
    
    .PHONY: external_lib $(COMPONENTS)
    $(external_lib): $(COMPONENTS)
    
    VARNAME = VAR
    $(COMPONENTS):
        @$(MAKE) -s -C $(source_dir)/project/component $(PROJECTVARS) \
    $(VARNAME)=$($(VARNAME)) $@
    
    make_c: VARNAME=OtherVar
    make_h: VARNAME=YetAnotherVar
    

    If you want to override several variables for some targets, that’s a little tricky…

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