I’m wondering how I can avoid some echo in a Makefile :
clean:
rm -fr *.o
this rule will print:
$>make clean
rm -fr *.o
$>
How can I avoid that?
I’m wondering how I can avoid some echo in a Makefile : clean: rm
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I’m wondering how I can avoid some echo in a Makefile :
clean:
rm -fr *.o
this rule will print:
$>make clean
rm -fr *.o
$>
How can I avoid that?
In fact I was looking for something else, adding this line to the Makefile :
while execute every step of the “clean” target silently.
Until someone point some drawback to this, I use this as my favourite solution!