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Asked: 2026-06-04T21:24:24+00:00

I’m working on the next release of my lock-free data structure library, using LL/SC

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I’m working on the next release of my lock-free data structure library, using LL/SC on ARM.

For my use-case of LL/SC, I need to use it with a single STR between the LDREX and STREX. (Rather than using it to emulate CAS.)

Now, I’ve written the code and this works.
What concerns me however is the possibility it may not always work.
I’ve read on PowerPC if you access the same cache line as the LL/SC target, you break the LL/SC.

So I’m thinking if my STR target is on the same cache line as my LL/SC target, then pow, I’m dead.

Now, the LL/SC target and STR targets are always in different malloc()s so the chance of them being directly in the same cache line is probably small (and I can guarantee this by padding the LL/SC target so it begins on a cache line boundary and fills that cache line).

But there could be false sharing, if the STR target is in just the right (wrong!) place in memory.

Looking at the LDREX/STREX documentation, this describes exclusive access in terms of "the physical address". This implies register width granularity, not cache line width granularity.

And that’s my question – is LDREX/STREX sensitivity to memory access using register width granularity or cache line width granularity?

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1 Answer

  1. Editorial Team

    ARM uses Exclusive Monitors to implement exclusive access to memory via load-linked/store-conditional. [1] has all the details, of importance here I’d say is the following:

    Exclusives Reservation Granule

    When an exclusive monitor tags an address, the minimum region that can
    be tagged for exclusive access is called the Exclusives Reservation
    Granule (ERG). The ERG is implementation defined, in the range 8-2048
    bytes, in multiples of two bytes. Portable code must not assume
    anything about ERG size.

    So you’re kinda out of luck there as I see it. Most real implementations will probably keep a small value anyway, but it’s not guaranteed by the basic ARM architecture as far as I can tell, but maybe someone with more experience will find me wrong. 🙂
    Still, kinda all implementations out there of LL/SC are some form of weak-LL/SC, so you can almost never be completely sure that a store between the LL and the SC won’t kill the SC always, or most of the time, or maybe never… It’s just so much architecture and implementation dependent that I personally stick to using LL/SC to implement CAS in a tight loop and use that as usual and be done with it.

    [1] http://infocenter.arm.com/help/index.jsp?topic=/com.arm.doc.dht0008a/CJAGCFAF.html

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