I’m writing a makefile framework for a project. Say, I have a main.c in the top dir, and many subdirs each containing a C file. To link all the object files togoter, I assign a initial value in the top makefile:
export TARGET_LIST := main.o
And in each subdirs, I append them to the list:
# sub1/Makefile
TARGET := a.o
TARGET_LIST += $(TARGET)
When return to the top dir, the TARGET_LIST is still with main.o. I’m sure all subdirs are entered. Is there any good way to do this?
The top makefile:
all: main
export TOP_DIR = $(shell pwd)
export TARGET_LIST := main.o
SUBDIRS := a b c d
CFLAGS := -Iinc
all:main
main:main.o subdirs
cc $(TARGET_LIST) -o $@ $(CFLAGS)
subdirs: $(patsubst %, _dir_%, $(SUBDIRS))
$(patsubst %, _dir_%, $(SUBDIRS)) :
$(MAKE) -C $(patsubst _dir_%, %, $@) $(TGT)
The Rules.make:
all:$(TARGET)
%.o:%.c
@echo $(TARGET_LIST)
$(CC) -c $^ -o $@ $(CFLAGS) $(LDFLAGS)
The subdir makefile:
TARGET := a.o
TARGET_LIST += $(TARGET)
CFLAGS :=
LDFLAGS :=
include $(TOP_DIR)/Rules.make
Do yourself the favour, and use a high-level build system if you can. Almost anything is better than hand-written Makefiles. E.g. CMake, SCons or waf are some of the more popular alternatives.