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Home/ Questions/Q 7965513
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Editorial Team
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Editorial Team
Asked: June 4, 20262026-06-04T06:10:48+00:00 2026-06-04T06:10:48+00:00

In a codebase I reviewed, I found the following idiom. void notify(struct actor_t act)

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In a codebase I reviewed, I found the following idiom.

void notify(struct actor_t act) {
    write(act.pipe, "M", 1);
}
// thread A sending data to thread B
void send(byte *data) {
    global.data = data;
    notify(threadB);
}
// in thread B event loop
read(this.sock, &cmd, 1);
switch (cmd) {
    case 'M': use_data(global.data);break;
    ...
}

“Hold it”, I said to the author, a senior member of my team, “there’s no memory barrier here! You don’t guarantee that global.data will be flushed from the cache to main memory. If thread A and thread B will run in two different processors – this scheme might fail”.

The senior programmer grinned, and explained slowly, as if explaining his five years old boy how to tie his shoelaces: “Listen young boy, we’ve seen here many thread related bugs, in high load testing, and in real clients”, he paused to scratch his longish beard, “but we’ve never had a bug with this idiom”.

“But, it says in the book…”

“Quiet!”, he hushed me promptly, “Maybe theoretically, it’s not guaranteed, but in practice, the fact you used a function call is effectively a memory barrier. The compiler will not reorder the instruction global.data = data, since it can’t know if anyone using it in the function call, and the x86 architecture will ensure that the other CPUs will see this piece of global data by the time thread B reads the command from the pipe. Rest assured, we have ample real world problems to worry about. We don’t need to invest extra effort in bogus theoretical problems.

“Rest assured my boy, in time you’ll understand to separate the real problem from the I-need-to-get-a-PhD non-problems.”

Is he correct? Is that really a non-issue in practice (say x86, x64 and ARM)?

It’s against everything I learned, but he does have a long beard and a really smart looks!

Extra points if you can show me a piece of code proving him wrong!

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1 Answer

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  1. Editorial Team
    Editorial Team
    2026-06-04T06:10:50+00:00Added an answer on June 4, 2026 at 6:10 am

    Memory barriers aren’t just to prevent instruction reordering. Even if instructions aren’t reordered it can still cause problems with cache coherence. As for the reordering – it depends on your compiler and settings. ICC is particularly agressive with reordering. MSVC w/ whole program optimization can be, too.

    If your shared data variable is declared as volatile, even though it’s not in the spec most compilers will generate a memory variable around reads and writes from the variable and prevent reordering. This is not the correct way of using volatile, nor what it was meant for.

    (If I had any votes left, I’d +1 your question for the narration.)

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