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In an embedded application, we have a table describing the various address ranges that are valid on our target board. This table is used to set up the MMU.
The RAM address range is marked as cacheable, but other regions are not. Why is that?
If a memory region is accessed by both hardware and software simultaneously (EX: hardware configuration register or scatter-gather list for DMA), this region must be defined as non-cached. For actual DMA, the memory buffer can be defined as cached, and in most cases, it is advisable for the buffer to be cached to allow the application level speedy access to that buffer. It’s the driver’s responsibility to flush/invalidate cache before passing the buffer to DMA or the application.
Small update, above must is not correct in case we have a specialized hardware, i.e. Cache Coherency Interconnect (CCI) which will synchronize access of various hardware blocks to memory.