Sign Up

Sign Up to our social questions and Answers Engine to ask questions, answer people’s questions, and connect with other people.

Have an account? Sign In

Have an account? Sign In Now

Sign In

Login to our social questions & Answers Engine to ask questions answer people’s questions & connect with other people.

Sign Up Here

Forgot Password?

Don't have account, Sign Up Here

Forgot Password

Lost your password? Please enter your email address. You will receive a link and will create a new password via email.

Have an account? Sign In Now

You must login to ask a question.

Forgot Password?

Need An Account, Sign Up Here

Please briefly explain why you feel this question should be reported.

Please briefly explain why you feel this answer should be reported.

Please briefly explain why you feel this user should be reported.

Sign InSign Up

The Archive Base

The Archive Base Logo The Archive Base Logo

The Archive Base Navigation

  • Home
  • SEARCH
  • About Us
  • Blog
  • Contact Us
Search
Ask A Question

Mobile menu

Close
Ask a Question
  • Home
  • Add group
  • Groups page
  • Feed
  • User Profile
  • Communities
  • Questions
    • New Questions
    • Trending Questions
    • Must read Questions
    • Hot Questions
  • Polls
  • Tags
  • Badges
  • Buy Points
  • Users
  • Help
  • Buy Theme
  • SEARCH
Home/ Questions/Q 8593717
In Process

The Archive Base Latest Questions

Editorial Team
  • 0
Editorial Team
Asked: June 12, 20262026-06-12T00:03:18+00:00 2026-06-12T00:03:18+00:00

In Conveyor architecture before execution instructions, they are broken down into smaller ones. So

  • 0

In Conveyor architecture before execution instructions, they are broken down into smaller ones. So they run much faster. But before instruction executed the whole, is not possible to execute the following instruction addressing to the same registers.
Is that right, to optimize the order of the instructions that would appeal to the same register(or RAM cell), to these instructions were located as far away from each other as possible?
Or no sense in this, because the compiler it self optimizes this way?

For example:

int a = 1, b = 2, c = 3;
a *= a;
b *= a;  // stop and waiting for the end of calculating (a)
c *= c;

Optimized:

int a = 1, b = 2, c = 3;
a *= a;
c *= c;  // calculating (a), but we don't need this and don't stop
b *= a;
  • 1 1 Answer
  • 0 Views
  • 0 Followers
  • 0
Share
  • Facebook
  • Report

Leave an answer
Cancel reply

You must login to add an answer.

Forgot Password?

Need An Account, Sign Up Here

1 Answer

  • Voted
  • Oldest
  • Recent
  • Random
  1. Editorial Team
    Editorial Team
    2026-06-12T00:03:19+00:00Added an answer on June 12, 2026 at 12:03 am

    It obviously depends on your compiler and architecture. Modern X86 processors support out of order execution, which means the processor doesn’t actually need to execute the instructions in order. Instead it will read a few instructions ahead (actually it isn’t even that few) and reorder them for better performance before execution. This means that this optimization is really not necessary for out of order cpus, since the actual execution order isn’t dependent on the order of the instructions in the code.

    For in order architectures (e.g. Cell) the order of instructions matters. However a properly optimizing compiler is quite likely to be able to do this reordering it self in many cases (that is as long as it can prove, that this won’t change the behaviour of the code). The main scenarios where it will likely fail to do so is, if pointers (or volatile variables) are involved, since in most cases the compiler can’t prove that different pointers don’t point to the same variable. Things like __restrict can help in that case.

    Another point to consider is, that in many cases the latency of things like an integer multiplication will not really have an effect on the runtime, since for many programs the performance is more limited by memory access. In cases where it does make a difference, it might be more useful to think about using simd and/or multithreading to optimize the code, then to think about instruction placement.

    In conclusion I would say that this kind of optimization isn’t really useful in a compiled language (When writing assembly the situation can be different), since both the cpu and the compiler might change the order anyways and it may not even make a difference. That doesn’t mean that there aren’t situations where this kind of optimization is useful, but that is really only in the most critical code paths, when it has been proven that the compiler/cpu isn’t up to the task.

    • 0
    • Reply
    • Share
      Share
      • Share on Facebook
      • Share on Twitter
      • Share on LinkedIn
      • Share on WhatsApp
      • Report

Sidebar

Related Questions

At work, we purchased a package of sensors that count items as they pass
Background: We are planning to use cameras on a conveyor system to count objects.
I'm using cpanm to install Perl modules, but I can't install Thread::Pool for some
I know that the Conveyor belt slideshow script (http://www.dynamicdrive.com/dynamicindex14/leftrightslide.htm) runs perfectly. What I want
In PHP, if I build a factory inspection program with a conveyor belt where
I am trying to put a table between rows of another table . But
What I'm trying to do is to implement something like the fruit machine scroll
This is a long shot, so if it's not possible, let me know. Basically,
I need some advice as to how to approach a project I am getting
I am using the jQuery UI slider and trying to show a div when

Explore

  • Home
  • Add group
  • Groups page
  • Communities
  • Questions
    • New Questions
    • Trending Questions
    • Must read Questions
    • Hot Questions
  • Polls
  • Tags
  • Badges
  • Users
  • Help
  • SEARCH

Footer

© 2021 The Archive Base. All Rights Reserved
With Love by The Archive Base

Insert/edit link

Enter the destination URL

Or link to existing content

    No search term specified. Showing recent items. Search or use up and down arrow keys to select an item.