Sign Up

Sign Up to our social questions and Answers Engine to ask questions, answer people’s questions, and connect with other people.

Have an account? Sign In

Have an account? Sign In Now

Sign In

Login to our social questions & Answers Engine to ask questions answer people’s questions & connect with other people.

Sign Up Here

Forgot Password?

Don't have account, Sign Up Here

Forgot Password

Lost your password? Please enter your email address. You will receive a link and will create a new password via email.

Have an account? Sign In Now

You must login to ask a question.

Forgot Password?

Need An Account, Sign Up Here

Please briefly explain why you feel this question should be reported.

Please briefly explain why you feel this answer should be reported.

Please briefly explain why you feel this user should be reported.

Sign InSign Up

The Archive Base

The Archive Base Logo The Archive Base Logo

The Archive Base Navigation

  • SEARCH
  • Home
  • About Us
  • Blog
  • Contact Us
Search
Ask A Question

Mobile menu

Close
Ask a Question
  • Home
  • Add group
  • Groups page
  • Feed
  • User Profile
  • Communities
  • Questions
    • New Questions
    • Trending Questions
    • Must read Questions
    • Hot Questions
  • Polls
  • Tags
  • Badges
  • Buy Points
  • Users
  • Help
  • Buy Theme
  • SEARCH
Home/ Questions/Q 8385463
In Process

The Archive Base Latest Questions

Editorial Team
  • 0
Editorial Team
Asked: June 9, 20262026-06-09T17:40:40+00:00 2026-06-09T17:40:40+00:00

In the Intel documentation Architectures Software Developer’s Manual Vol 2A , Table 2-4 shows

  • 0

In the Intel documentation “Architectures Software Developer’s Manual Vol 2A”, Table 2-4 shows the significance of the REX prefix’s bits.

Can someone explain to me how to interpret when W=0? It says 0 = Operand size determined by CS.D but I don’t understand what CS.D means.

  • 1 1 Answer
  • 0 Views
  • 0 Followers
  • 0
Share
  • Facebook
  • Report

Leave an answer
Cancel reply

You must login to add an answer.

Forgot Password?

Need An Account, Sign Up Here

1 Answer

  • Voted
  • Oldest
  • Recent
  • Random
  1. Editorial Team
    Editorial Team
    2026-06-09T17:40:41+00:00Added an answer on June 9, 2026 at 5:40 pm

    CS.D stands for the “default operation size” field of the segment descriptor associated with the current Code Segment. This controls the default size of addresses and operands, and can be set to default to 16 or 32 bit operand-size.

    In 64-bit aka long mode (CS.L=1), the only valid setting for CS.D = 32-bit, so a REX prefix with the W bit cleared leaves the default operand size at 32-bit. (An operand-size prefix can override the operand-size down to 16).

    The default address size in long mode is 64-bit (an address-size prefix on an instruction overrides it to 32).


    Segment descriptors are described in detail in Volume 3A – System Programming Guide, Part 1, chapter 3.4.5 Segment Descriptors.

    The effects of the D field are also discussed in Volume 1 – Basic Architecture, chapter 3.6 Operand-size and address-size attributes.

    • 0
    • Reply
    • Share
      Share
      • Share on Facebook
      • Share on Twitter
      • Share on LinkedIn
      • Share on WhatsApp
      • Report

Sidebar

Related Questions

I'm studying the Intel's IA-32 software developer manual. In particular, I'm reading the following
I read the Intel manual and found there is a lock prefix for instructions,
Because of the Intel Turbo Boost technology, I can't trust the CPU frequency written
In the Intel documentation manuals, I see references to 00+ multiple places, but no
I'm using JavaScript Places Library http://code.google.com/intl/en/apis/maps/documentation/javascript/places.html However, I can't find how to set the
Intel's documentation of MONITOR says: The MONITOR instruction arms address monitoring hardware using an
According to ADC documentation: You can access Open Firmware this by holding down Command-Option-O-F
I'm going through the Intel processor documentation and writing some basic assembly code at
The Intel ISA reference documentation for this instruction is clear: VPBLENDVB xmm1, xmm2, xmm3/m128,
Intel's 32-bit processors such as Pentium have 64-bit wide data bus and therefore fetch

Explore

  • Home
  • Add group
  • Groups page
  • Communities
  • Questions
    • New Questions
    • Trending Questions
    • Must read Questions
    • Hot Questions
  • Polls
  • Tags
  • Badges
  • Users
  • Help
  • SEARCH

Footer

© 2021 The Archive Base. All Rights Reserved
With Love by The Archive Base

Insert/edit link

Enter the destination URL

Or link to existing content

    No search term specified. Showing recent items. Search or use up and down arrow keys to select an item.