Is there a TAP (Test Anything Protocol) implementation for VHDL? It would be nice because then I could use prove to check my results automatically. There are also nice formatting swuites such as smolder that can process it output. You might ask why not use assertions. Partly TAP gives me some good reporting such as number of files and number of tests. I’m looking for a minimal implentation with number of tests at the beginning and end and the ok, diag and fail functions. is() would really nice, but not necessary. I could write this, but why reinvent the wheel.
This is the question as in this question but for VHDL instead of Verilog.
I wrote one that I’ve used a lot, but I’ve never distributed it. Here it is (the not-included base_pkg mostly has to_string() implementations for everything).