Question

Is there a way to speed up Xilinx ISE build process? I have multiple verilog HDL files in my project. Sometimes I implement a minor change in at a place in one file. However the build time is same as if the whole project were changed. I think software does not offer any advantage for already build modules.

I know its hardware, but is there some way out. I am really trouble with my slow progress. Any other tips to make the process will be appreciated.

Yours Truely

Abu Bakar

Answer 1

There are quite a few things you can do to speed up an FPGA build. Among them:
– floorplanning
– design partitioning (Xilinx and Altera have some differences)
– adding false paths and mulitcycle paths constraints
– playing with synthesis and physical implementation tool options
– choice of the reset scheme can also affect the build time
– not over-constraining timing

I discuss this very topic in more detail in my book.

Thanks.