Question

I’ve got a make file that generates multiple targets. Something like:

target-a: target-a.src target-include.src
        @$(BUILD_TOOL) -f $< -o $@
target-b: target-b.src target-include.src
        @$(BUILD_TOOL) -f $< -o $@
target-c: target-c.src target-include.src
        @$(BUILD_TOOL) -f $< -o $@

The actual build process (abbreviated as $(BUILD_TOOL) above) is a multiple line thing involving compilers, scripts and various whatnot, but suffice to say, the build process acts on the first target dependency ($<) and produces the output target ($@).

This is quite unwieldly. Would what I’ve got below be considered a safe way to replace the above (using a pattern rule that doesn’t have a suffix)?

all: target-a target-b target-c

% : %.src target-include.src
        @$(BUILD_TOOL) -f $< -o $@

The make tool is GNU, and I’m content to use it’s powerful extensions.

Answer 1

If target is a literal string, renierpost’s solution is very good. If it isn’t (or even if it is) this will work:

TARGETS := target-a target-b target-c

all: $(TARGETS)

$(TARGETS): % : %.src target-include.src
    @$(BUILD_TOOL) -f $< -o $@

Note that this rule will not build targets you did not intend, not even target-include.