Question

I’ve got a problem with a pseudo random number generators with a counter to check if I’m dealling with irreducible polynomial. the geenrator is working without problems but the counter doesn’t if I try to use it as a sub-module. any idea ??

-- x^6 + x^5 + x^3 + x^2 + 1

Library IEEE;
use ieee.numeric_std.all;

use IEEE.STD_LOGIC_1164.ALL;

use ieee.std_logic_unsigned.all;


entity EPZG is
   port (CLK:       in std_logic;                      
         EQ:        out bit_vector(5 downto 0);  
             A :        out bit );
 end EPZG;

 architecture behaviour of EPZG is 
 component Counter is port ( CLK, RESET : in std_logic;
   result: out bit_vector(5 downto 0)); 
 end component;

signal SZ: bit; 
signal SEQ : bit_vector(5 downto 0); 
signal CNT_RESET : std_logic; 
signal CNT_RESULT : bit_vector(5 downto 0);
begin 
  SZ <= '1';
  PZG : process(CLK)
  begin
  CNT_RESET <= '1';

    if (CLK'event and CLK ='1') then
       SEQ(0) <= SZ xor SEQ(5);
       SEQ(1) <= SEQ(0);
       SEQ(2) <= SEQ(1) xor SEQ(5);
       SEQ(3) <= SEQ(2) xor SEQ(5);
       SEQ(4) <= SEQ(3);
       SEQ(5) <= SEQ(4) xor SEQ(5);
    end if;
end process PZG;
EQ <= SEQ;
CNT: Counter port map ( CLK , RESET =>CNT_RESET,result =>CNT_RESULT);
end behaviour;

the counter Code

1. Library IEEE;
   use IEEE.STD_LOGIC_1164.ALL;
   use ieee.std_logic_unsigned.all;

   entity Counter is port 
   (CLK, RESET : in std_logic;
     result: out bit_vector(5 downto 0));
   end Counter;
   
   architecture BEHAVIOUR of Counter is
     signal pre_counter: std_logic_vector(5 downto 0);
     begin 
     REG : process(CLK, RESET)
     begin
     if(CLK'event and CLK = '1') then 
        if (RESET = '0') then
            pre_counter <= (others =>'0');
        else
     pre_counter <= pre_counter +1 ;
       end if;
     end if; 
   end process;
   result <= To_bitvector (pre_counter);
   end BEHAVIOUR;
   

Answer 1

Okay then, another try. Your counter module never gets reset, so pre_counter is never initialized – which will give you undefined results in simulation at least. Either generate a reset for it in your top-level code, or initialize it as:

signal pre_counter: std_logic_vector(5 downto 0) := (others => '0');

Also, your process code in your counter module could use a few tweaks. The process sensitivity list contains both clk and reset, yet your process uses a synchronous reset. You should make your processes either with a synchronous reset and only clk in the sensitivity list:

process(clk)
begin
  if(rising_edge(clk)) then
    if(reset = '1') then
    (...)

or with an asynchronous reset and both clk and reset in the sensitivity list:

process(clk, reset)
begin
  if(reset = '1') then
    (...)
  elsif(rising_edge(clk)) then
    (...)

Also notice the use of the rising_edge() function, which is the “modern” way of checking for an edge.