Question

I’ve this:

include makefile_vars.mk

# Target
TARGET := $(OBJ)/$(TARGETNAME)

# Move objects to ../Obj
OBJECTS := $(addsuffix .obj,$(SOURCES))
override OBJECTS := $(OBJECTS:$(SRC)/%.obj=$(OBJ)/%.obj)

# Objects o
OBJ_INC_DIRS := $(sort $(dir $(OBJECTS)))

# Target 
all: $(TARGET)

$(TARGET): $(OBJECTS)

# Objects
$(OBJ)/%.c.obj: $(SRC)/%.c | $(OBJ_INC_DIRS)
    @echo Compiling $(<F) ...

$(OBJ)/%.a66.obj: $(SRC)/%.a66 | $(OBJ_INC_DIRS)
    @echo Compiling $(<F) ...

$(OBJ_INC_DIRS): 
    mkdir -p $@

The first time I launch it, it says me that there is no rule to make the target MyFile.c.obj, when running again (whitout modifying anything) the rule is found and the compilation goes on.

What am I doing wrong?

Answer 1

I’m not sure that this will work, but I would move $(OBJ_INC_DIRS) order-only prerequisite out from the pattern rules:

$(OBJECTS) : | $(OBJ_INC_DIRS)

$(OBJ)/%.c.obj: $(SRC)/%.c
    @echo Compiling $(<F) ...

...