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Many VMS, JVM/LLVM/… have JITs — as the code is being interpreted, x86 instructions are created on the fly and executed.
If there something similar to this for FPGAS? Is there someway where as an FPGA is running, I reconfigure it? [If so, please provide project / paper links. If not, what is the technology bottleneck that prevents this from happening?]
Thanks!
“partial reconfiguration” may be the phrase to Google for.