Me again with another innocuous Z80 question 🙂 The way my emulator core is currently structured, I am incrementing the lower 7 bits of the memory refresh register every time an opcode byte is fetched from memory – this means for multi-byte instructions, such as those that begin DD or FD, I am incrementing the register twice – or in the instance of an instruction such as RLC (IX+d) three times (as it is laid out opcode1-opcode2-d-opcode3).
Is this correct? I am unsure – the Z80 manual is a little unclear on this, as it says that CPDR (a two byte instruction) increments it twice, however the ‘Memory Refresh Register’ section merely says it increments after each instruction fetch. I have noticed that J80 (an emulator I checked as I’m not sure about this) only increments after the first opcode byte of an instruction.
Which is correct? I guess it is not hugely important in any case, but it would be nice to know 🙂 Many thanks.
Regards,
Phil Potter
All references I can find online say that R is incremented once per instruction irrespective of its length.