Question

My make file has worked, up until I tried some variable substitution. %.o is not recognized.

I get make: * No rule to make target `%.o’, needed by `parser’. Stop.

CC=gcc
CFLAGS=-ansi -pedantic -Wall -ggdb3
PROJECT=project.c project.h
PARSER=parser.c parser.h
OBJ=project.o parser.o
#CFILE=project.c parser.c

#1 no problem
#parser: project.o parser.o
#  $(CC) $(CFLAGS) -o $@ $^

#2 no problem
#parser: $(OBJ)
#  $(CC) $(CFLAGS) -o $@ $^

#3 this fails
parser: %.o
   $(CC) $(CFLAGS) -o $@ $^

#parser: project.o parser.o
#  gcc -ansi -pedantic -Wall -ggdb -o parser project.o parser.o

project.o: $(PROJECT)
   $(CC) $(CFLAGS) -c $^

parser.o: $(PARSER)
   $(CC) $(CFLAGS) -c $^

clean:
   rm -f $(OBJ) parser

Answer 1

You’re not creating a pattern rule, since there is no % in the target name. As a result the % has no special meaning in the list of dependencies. It’s seen as a literal part of a file name; you can’t use it as a regular wildcard.