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Asked: 2026-05-16T22:00:59+00:00

Now , My doubt has changed to exact point after some long discussion in

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Now ,
My doubt has changed to exact point after some long discussion in this thread with dwelch.

“If you are wondering how the processor gets ready to execute the first instruction. its the way the logic is designed” HOW THE LOGIC IS DESIGNED? Can you give me more idea on this? Is there any document give me more details? Is the algorithm behind all architecture are same?

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  1. Editorial Team

    “If you are wondering how the processor
    gets ready to execute the first
    instruction. its the way the logic is
    designed” – HOW THE LOGIC IS DESIGNED?
    Can you give me more idea on this? Is
    there any document give me more
    details? Is the algorithm behind all
    architecture are same?

    conceptually, the Program Counter (PC) may be thought of as having an increment logic that is tied to the instuction cycle. it may be thought of as the following logic that is executed at the end of each instruction cycle.

    if (RESET)         //reset pin input is asserted
    PC = 0x0000;   // or any other predetermined value
else
    PC = PC + length(currentInstruction);

    for ease of understanding, think of a processor which executes 1 instruction in each clock cycle. in addition consider all instuctions to be of the same size (4 bytes as in arm).

    then the logic becomes even simpler

    if (RESET)
    PC = 0x0000;
else
    PC = PC + 4;

    now this logical decision is simple enough to implemented as a digital logic circuit using gates, which has inputs – RESET, and PC and output – PC, and clocked by the processor clock.
    as long as the RESET signal is asserted, there could be additional logic that disables the execution pipeline and the fetch circuit.

    while the RESET is asserted, the PC is loaded with the restart address.

    now the responsibility to assert and release the RESET signal lies with the reset circuitry which may choose to do so only after it receives the POWERGOOD signal and/or CLOCKSTABLE signal.

    the clockgenerator outputs the CLOCKSTABLE after the clock signal is stable and usable.

    the POWERGOOD signal is asserted by the power circuitry after the voltage has stabilized.

    all these signals may not be present or used in a particular platform.
    the RESET signal is usually found on all processors.

    once the RESET signal is released, the execution pipeline is enabled and
    the execution logic initiates a FETCH from that address.

    books on digital logic design will usually have this kind of info. and some example to show how to design an ALU.
    the PC incrementing algorithm behind each architecture will be similar(in concept) but has to take care of peculiarities of the processor design.

    if the processor supports two differnt restart addresses depending upon a jumper setting, it can be usually achieved by having an additional pin on the processor which is connected to a jumper which may pull it to logic 1 or 0.

    now the PC increment logic becomes,

    if (RESET)
    if(RESETADDRESSJUMPER)
         PC = 0x0000;
    else
         PC = 0xfff0;
else
    PC = PC + 4;

    similarly, it is possible to define any complex logic to reset the processor required by the processor architecture.

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