Question

Ok another question in VHDL. Below is my code. Suppose that I want my input stored in ram. And lets say I want to add two of them. (do not give emphasis on it, later on it will be replaced). This is my code:

library IEEE;
use IEEE.STD_LOGIC_1164.all;
USE ieee.numeric_std.ALL;

use work.my_package.all;

entity landmark_1 is
  generic
        (data_length :integer := 8;
        address_length:integer:=3 );
        port ( clk:in std_logic;
        vin:in std_logic;
        rst:in std_logic;
        flag: in std_logic;
        din: in signed(data_length -1 downto 0);
        done: out std_logic
        );
end landmark_1;

architecture TB_ARCHITECTURE of landmark_1 is


component ram IS
    generic
    (
        ADDRESS_WIDTH   : integer := 4;
        DATA_WIDTH  : integer := 8
    );
    port
    (
        clock           : IN  std_logic;
        data            : IN  signed(DATA_WIDTH - 1 DOWNTO 0);
        write_address           : IN  unsigned(ADDRESS_WIDTH - 1 DOWNTO 0);
        read_address            : IN  unsigned(ADDRESS_WIDTH - 1 DOWNTO 0);
        we          : IN  std_logic;
        q           : OUT signed(DATA_WIDTH - 1 DOWNTO 0)
    );
end component;

signal inp1,inp2: matrix1_t(0 to address_length);
signal out_temp: signed(data_length-1 downto 0);
signal k:unsigned(address_length-1 downto 0);

signal i: integer range 0 to 100:=0;
begin

read1:ram generic map( ADDRESS_WIDTH=>address_length, DATA_WIDTH=>data_length) port map (clk,din,k,k,vin,out_temp);
inp1(i)<=out_temp;

process (clk)
  begin
  if (clk'event and clk='1') then 
    if (flag='1') then out_temp<=inp1(0)+inp1(1);
    end if;
  end if; 
end process ;   

end TB_ARCHITECTURE; 

Below are my questions:

1. Why to use that ram and not just do inp(i)<=din; . I think that it will help synthesizer understand that this is a ram, but what else? Moreover, do I need inp1 registers. And if I a going to use them, again why use ram as an intermediate?
2. If inp1 is unnecessary, how I am going to fetch these two elements in my process? I mean I need something like ram(address1)+ram(address2), right?

Below is my ram_code:

LIBRARY ieee;
USE ieee.std_logic_1164.ALL;
USE ieee.numeric_std.ALL;

ENTITY ram IS
    GENERIC
    (
        ADDRESS_WIDTH   : integer := 4;
        DATA_WIDTH  : integer := 8
    );
    PORT
    (
        clock           : IN  std_logic;
        data            : IN  signed(DATA_WIDTH - 1 DOWNTO 0);
        write_address           : IN  unsigned(ADDRESS_WIDTH - 1 DOWNTO 0);
        read_address            : IN  unsigned(ADDRESS_WIDTH - 1 DOWNTO 0);
        we          : IN  std_logic;
        q           : OUT signed(DATA_WIDTH - 1 DOWNTO 0)
    );
END ram;

ARCHITECTURE rtl OF ram IS
    TYPE RAM IS ARRAY(0 TO 2 ** ADDRESS_WIDTH - 1) OF signed(DATA_WIDTH - 1 DOWNTO 0);

    SIGNAL ram_block : RAM;
BEGIN
    PROCESS (clock)
    BEGIN
        IF (clock'event AND clock = '1') THEN
            IF (we = '1') THEN
                ram_block(to_integer(unsigned(write_address))) <= data;
            END IF;

            q <= ram_block(to_integer(unsigned(read_address)));
        END IF;
    END PROCESS;
END rtl;

3.can anyone tell me why the q (output) is estimated one clock later?

EDIT: To sum up,I was told that I should use a ram and this is my implementation. The question is what I have gained by changing my inp1(i)<=din; when I inserted the ram model. And there fore how can I use it? (before using the ram I waws just wrote inp1(i)+inp2(i+1) for example).

EDIT2: PACKAGE FOR TYPES.

library IEEE;
use IEEE.std_logic_1164.all;
use ieee.numeric_std.all;

package my_package is
    type matrix1_t is array(integer range<>) of signed(7 downto 0);
    type big_matrix is array(integer range<>) of signed(23 downto 0);
    type matrix2d is array (integer range<>) of big_matrix(0 to 3);

end my_package;

Answer 1

Why to use that ram and not just do inp(i)<=din;

In real world designs you use RAMs to store large amounts of data because they are smaller (physically, on the chip) that arrays of flip flops. During the synthesis process the RAM is replaced by one from your vendor’s library. This RAM looks rather small, but I’m guessing you’ve been told to use one as an exercise.

Moreover, do I need inp1 registers. And if I a going to use them, again why use ram as an intermediate?

I’m not quite sure what imp1 is, as I don’t know what a matrix_t is, but I’m guessing it’s a register version of the RAM. In which case it’s redundant.

If inp1 is unnecessary, how I am going to fetch these two elements in my process? I mean I need something like ram(address1)+ram(address2), right?

…and there’s the real issue. You need to ask yourself ‘If you can’t read more that one thing in a cycle, how do you add two numbers?’

can anyone tell me why the q (output) is estimated one clock later?

Because that’s how RAMs work. You apply an address in one cycle, and the data appears some cycles later (normally one, but not always)

These are real issues that you’ll face in real designs. RAMs are necessary because of their smaller size. You need to know the issues that surround using them and how to work with them.