Question

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How do you force a makefile to rebuild a target

I’m using a slightly modified version of zedshaw’s makefile, but when I run it it doesn’t recompile .o files.

I just spent 2 hours debugging only to find out make was looking at the existing object files and simply not recompiling them.

How do I force make to recompile $(OBJECTS) in future? Is there a way to do it without adding the clean target before all?

Edit: For clarity: Make is supposed to recompile automatically if something in the source has been changed, this isn’t working for the $(OBJECTS) so I either need to force recompiling them or find out why it’s not doing it itself.

Edit 2: After copying the whole folder and diffing it at different times I realized that make was correctly seeing all but one dependency. The problem is in the following point:

tests: LDLIBS += $(TARGET)
tests: $(TESTS)

Make doesn’t recognize things under LDLIBS as dependencies so I added:

$(TESTS): $(TARGET)

Which resolved the issue. Since Jens called it in the comments I’m going to mark his answer as accepted.

CFLAGS=-g -O2 -Wall -Wextra -Isrc -rdynamic -DNDEBUG $(OPTFLAGS)
LDLIBS=-ldl $(OPTLIBS)
PREFIX?=/usr/local

SOURCES=$(wildcard src/**/*.c src/*.c)
OBJECTS=$(patsubst %.c,%.o,$(SOURCES))

TEST_SRC=$(wildcard tests/*_tests.c)
TESTS=$(patsubst %.c,%,$(TEST_SRC))

TARGET=build/liblcthw.a
SO_TARGET=$(patsubst %.a,%.so,$(TARGET))

# The Target Build
all: cls $(TARGET) $(SO_TARGET) tests

dev: CFLAGS=-g -Wall -Isrc -Wall -Wextra $(OPTFLAGS)
dev: all

$(TARGET): CFLAGS += -fPIC
$(TARGET): build $(OBJECTS)
    ar rcs $@ $(OBJECTS)
    ranlib $@

$(SO_TARGET): $(TARGET) $(OBJECTS)
    $(CC) -shared -o $@ $(OBJECTS)

build:
    @mkdir -p build
    @mkdir -p bin

# The Unit Tests
.PHONY: tests
tests: LDLIBS += $(TARGET)
tests: $(TESTS)
    sh ./tests/runtests.sh

valgrind:
    VALGRIND="valgrind --log-file=/tmp/valgrind-%p.log" $(MAKE)

# The Cleaner
clean: cls
    rm -rf build $(OBJECTS) $(TESTS)
    rm -f tests/tests.log
    find . -name "*.gc*" -exec rm {} \;
    rm -rf `find . -name "*.dSYM" -print`

# The Install
install: all
    install -d $(DESTDIR)/$(PREFIX)/lib/
    install $(TARGET) $(DESTDIR)/$(PREFIX)/lib/

# The Checker
BADFUNCS='[^_.>a-zA-Z0-9](str(n?cpy|n?cat|xfrm|n?dup|str|pbrk|tok|_)|stpn?cpy|a?sn?printf|byte_)'
check:
    @echo Files with potentially dangerous functions.
    @egrep $(BADFUNCS) $(SOURCES) || true

# Clear screen for unspammy terminals
cls:
    clear

Answer 1

How do I force make to recompile?

Two options:

1. touch all source files
2. If you are using GNU make, make --always-make