Question

Say I have an entity:

entity myblock is
    port(
        input1 : std_logic_vector(15 downto 0);
        input2 : std_logic_vector(15 downto 0);
        input3 : std_logic_vector(15 downto 0);
        -- ...
        output : std_logic_vector(15 downto 0);
    );
end myblock;

I now want to make the size of the inputs generic, so I might do:

entity myblock is
    generic(
        WIDTH : natural;
    );
    port(
        input1 : std_logic_vector(WIDTH-1 downto 0);
        input2 : std_logic_vector(WIDTH-1 downto 0);
        input3 : std_logic_vector(WIDTH-1 downto 0);
        -- ...
        output : std_logic_vector(WIDTH-1 downto 0);
    );
end myblock;

Ideally I’d like to simplify this a bit and have, say:

subtype calc_data is std_logic_vector(WIDTH-1 downto 0);
port(
    input1 : calc_data;
    input2 : calc_data;
    input3 : calc_data;
    -- ...
    output : calc_data;
);

In this case it’s a very simple example, and the benefit is not huge. In more complex cases, though, it would really help.

Is this possible in VHDL?

Answer 1

You can name more than one port using a single type specification:

entity myblock is
    generic(
        WIDTH : natural;
    );
    port(
        input1, input2, input3 : in std_logic_vector(WIDTH-1 downto 0);
        -- ...
        output : out std_logic_vector(WIDTH-1 downto 0);
    );
end myblock;