Question

So I have something like this:

module top (..., out,...);
...
output [0:1] out;
wire [0:3] out;
...
endmodule

Is this correct verilog? If so, is the correct behavior of this a 2 bit out port?

Answer 1

The verilog 2001 quick reference guide (section 5.2) says this:

• Port/data type connection rules:
The port range and data type range must be the same (if different, some
software tools will use the data type size instead of reporting an error).

So I’ll say it’s not correct.