Question

So I’m using an algorithm to create a structure like the one in the link (http://ars.els-cdn.com/content/image/1-s2.0-S0140366499000031-gr1.gif). So I created function which will determine where to jump to next.
In my VHDL switch architecture I’m trying to use a generate statement to define nodes and map their ports appropriately however when I synthesize it says
” “banyan” cannot be used in this expression” (banyan is a function in a library). Below is some example code:

INPUT: IF ( l = 1 ) GENERATE 
            NODE_Element : BN PORT MAP( 
                                                clk, reset, 
                                                Input((2*n)-1), 
                                                Input((2*n)), 
                                                SyncIn, 
                                                con(l+1,Banyan(l,n),BanyanPort(l,n)), 
                                                con(l+1,Banyan(l,n),BanyanPort(l,n)), 
                                                sync(l+1,n)
                                            ); --GENERIC MAP(...)
        END GENERATE INPUT;

Has anyone got an idea how to solve this… it seems fundamental but I could find a solution.

Answer 1

Looks like the problem isn’t the generate, but the port map. There are some restrictions on what you can do in a port map, and many tools (you don’t say which synth tool this is!) impose severe restrictions of their own.

I would suggest assigning the function result to a temporary signal, and using that signal in the port map.

INPUT: IF l = 1 GENERATE 
Banyan1     <= Banyan(l,n);
BanyanPort1 <= BanyanPort(l,n);
Con1        <= con(l+1,Banyan(l,n),BanyanPort(l,n)); 

 NODE_Element : BN PORT MAP( 
                              clk, reset, 
                              Con1, 
                           );
END GENERATE INPUT; 

You may find that not all of these changes are necessary; probably moving con(…) out of the port map is enough.