Question

The datasheet of my microcontroller C8051F120 is clear on when it comes to reading the 16 bit value PCA0L and PCA0H:

“Reading PCA0L automatically latches the value of PCA0H into a “snapshot” register; the following PCA0H read accesses this “snapshot” register. Reading the PCA0L Register first guarantees an accurate reading of the entire 16-bit PCA0 counter.”

However, I did not find a similar statement regarding the TMRnL and TMRnH registers. I remember on an Atmega128CAN90, I have used the following

unsigned char chL,chH;
#asm("cli")
chL=TCNT3L;
chH=TCNT3H;
#asm("sei")

Does anybody knows if the above quote also holds for the TMRnL and TMRnH registers of the C8051F120? Or, what is a safe way to get a consistent reading? Do interrupts need to be disabled?
Thanks for your help!

Answer 1

Page 116 of the datasheet says:

The TCNTn, OCRnx, and ICRn are 16-bit registers that can be accessed by the AVR CPU via the 8-bit data bus. The 16-bit register must be byte accessed using two read or write operations. Each 16-bit timer has a single 8-bit register for temporary storing of the high byte of the 16-bit access. The same temporary register is shared between all 16-bit registers within each 16-bit timer. Accessing the low byte triggers the 16-bit read or write operation. When the low byte of a 16-bit register is written by the CPU, the high byte stored in the temporary register, and the low byte written are both copied into the 16-bit register in the same clock cycle. When the low byte of a 16-bit register is read by the CPU, the high byte of the 16-bit register is copied into the temporary register in the same clock cycle as the low byte is read.

So it does appear a similar thing is happening.