Question

the task is to make a 4-Bit Multiplier that uses FSM. the steps would be 1) multiply 2) shift 3) add.

  1011   (this is 11 in binary)
 x 1110   (this is 14 in binary)
 ======
   0000   (this is 1011 x 0)
  1011    (this is 1011 x 1, shifted 1 position to the left)
 1011     (this is 1011 x 1, shifted 2 positions to the left)
1011      (this is 1011 x 1, shifted three positions to the left)
======

10011010 (this is 154 in binary)

http://en.wikipedia.org/wiki/Binary_multiplier

here are my codes:

library IEEE;
use IEEE.STD_LOGIC_1164.ALL;
use IEEE.STD_LOGIC_ARITH.ALL;
use IEEE.STD_LOGIC_UNSIGNED.ALL;

entity test is
    Port ( CLK : in  STD_LOGIC;
       RESET : in  STD_LOGIC;
       Input : in  STD_LOGIC_VECTOR (3 downto 0);
       Confirm : in  STD_LOGIC;
       Output : out  STD_LOGIC_VECTOR (7 downto 0));
end test;

architecture Behavioral of test is

type state is (R,S0,S1,S2,S3,S4);
signal pstate, nstate: state;
signal A_sig, B_sig: STD_LOGIC_VECTOR(3 downto 0);

begin
process(pstate,Confirm,Input)
variable temp_var: STD_LOGIC_VECTOR(3 downto 0);
variable tempMult_var,tempProd_var: STD_LOGIC_VECTOR(7 downto 0);
begin
    case pstate is
        when R =>
            nstate <= S0;
            tempMult_var := (others => '0');
            tempProd_var := (others => '0');

            A_sig <= (others => '0');
            B_sig <= (others => '0');

            Output <= (others => '0');
        when S0 =>
            nstate <= S0;

            if (Confirm = '1') then
                A_sig <= Input;
                nstate <= S1;
            end if;
        when S1 =>
            nstate <= S1;

            if (Confirm = '0') then
                nstate <= S2;
            end if;
        when S2 =>
            nstate <= S2;

            if (Confirm = '1') then
                B_sig <= Input;
                nstate <= S3;
            end if;
        when S3 =>
            nstate <= S3;

            if (Confirm = '0') then
                nstate <= S4;
            end if;
        when S4 =>
            nstate <= S0;

            for x in 0 to 3 loop
                temp_var := (A_sig AND (B_sig(x)&B_sig(x)&B_sig(x)&B_sig(x) ) );
                tempMult_var := "0000" & temp_var;
                if (x=0) then tempMult_var := tempMult_var;
                    elsif (x=1) then tempMult_var := tempMult_var(6 downto 0)&"0";
                    elsif (x=2) then tempMult_var := tempMult_var(5 downto 0)&"00";
                    elsif (x=3) then tempMult_var := tempMult_var(4 downto 0)&"000";        
                end if;
                tempProd_var := tempProd_var + tempMult_var;
            end loop;

            Output <= tempProd_var;
            tempProd_var := (others => '0');
    end case;
end process;

process(CLK,RESET)
begin
    if RESET = '1' then
        pstate <= R;
    elsif rising_edge(CLK) then
        pstate <= nstate;
    end if;
end process;
end Behavioral;

here are the warnings

after "Synthesize - XST"
WARNING:Xst - Property "use_dsp48" is not applicable for this technology.
WARNING:Xst:737 - Found 4-bit latch for signal <B_sig>.
WARNING:Xst:737 - Found 8-bit latch for signal <Output>.
WARNING:Xst:737 - Found 4-bit latch for signal <A_sig>.

after "Implement Design"
WARNING:Route:447 - CLK Net:A_sig_not0001 may have excessive skew because 
WARNING:Route:447 - CLK Net:B_sig_not0001 may have excessive skew because 

after "Generate Programming File"
WARNING:PhysDesignRules:372 - Gated clock. Clock net A_sig_not0001 is sourced by
WARNING:PhysDesignRules:372 - Gated clock. Clock net B_sig_not0001 is sourced by
WARNING:PhysDesignRules:372 - Gated clock. Clock net Output_or0000 is sourced by

the simulations are correct but the actual board doesn’t have the correct output. what might be the problem?

Answer 1

My humble advice:

Combine your two processes into a single clocked process.

That way you avoid a whole category of asynchronous logic mistakes that are easy for a beginner to make to painful to track down.