Question

There is no synthesis error in the following code, but still not getting the output when I simulate it. cout is staying logic 1 all the time. Please can anybody help me out to find out whats wrong?

library IEEE;
use IEEE.STD_LOGIC_1164.ALL;
use IEEE.STD_LOGIC_ARITH.ALL;
use IEEE.STD_LOGIC_UNSIGNED.ALL;

entity divide_by_3 is
port (
  cout   :out std_logic; -- Output clock
  clk    :in  std_logic; -- Input clock
  reset  :in  std_logic  -- Input reset
 );
end divide_by_3;

architecture Behavioral of divide_by_3 is
  signal pos_cnt :std_logic_vector (1 downto 0);
  signal neg_cnt :std_logic_vector (1 downto 0);
begin

  process (clk, reset) 
    begin
      if (reset = '1') then
        pos_cnt <= (others=>'0');
      elsif (rising_edge(clk)) then
        if (pos_cnt = "10") then
          pos_cnt <= pos_cnt + '1';
        end if;
      end if;
    end process;

    process (clk, reset) begin
      if (reset = '1') then
        neg_cnt <= (others=>'0');
      elsif (falling_edge(clk)) then
        if (neg_cnt = "10") then
          neg_cnt <= neg_cnt + '1';
        end if;
      end if;
    end process;

    cout <= '1' when ((pos_cnt /= "10") and (neg_cnt /= "10")) else
    '0';
end Behavioral;

Answer 1

Your counter will never count because you do:

    if (neg_cnt = "10") then
      neg_cnt <= neg_cnt + '1';
    end if;

and

    if (pos_cnt = "10") then
      pos_cnt <= pos_cnt + '1';
    end if;

but both, pos_cnt and neg_cnt are reset to "00". I guess you might want to do something similar like:

    if (pos_cnt = "10") then
      pos_cnt <= (others => '0');
    else
      pos_cnt <= pos_cnt + '1';
    end if;