Question

This is a super naive question (I know), but I think that it will make for a good jumping off point into considering how the basic instruction set of a CPU actually gets carried out:

In a two’s complement system, you cannot invert the sign of the most negative number that your implementation can represent. The theoretical reason for this is obvious in that the negation of the most negative number would be out of the range of the implementation (the range is always something like
-128 to 127).

However, what actually happens when you try to carry out the negation operation on the most negative number is pretty strange. For example, in an 8 bit representation, the most negative number is -128, or 1000 0000 in binary. Normally, to negate a number you would flip all the bits and then add one. However, if you try to do this with -128 you end up with:

1000 0000 ->
0111 1111 ->
1000 0000

the same number that you started out with. For this reason, wikipedia calls it “the weird number”.

In that same wikipedia article, it says that the above negation

is detected as an overflow condition since there was a carry into but not out of the most-significant bit.

So my question is this:
A) What the heck does that mean? and
B) It seems like the CPU would need to perform an extra error checking step each and every time it carried out a basic arithmetic operation in order to avoid accidents relating to this negation, creating significant overhead. If that is the case, why not just truncate the range of numbers that can be represented to leave the weird number out (i.e. -127 to 127 for 8 bits)? If that isn’t the case, how can you implement such error checking without creating extra overhead?

Answer 1

It’s not that the CPU does another check, its that the transistors are arranged to notice when this happens. And they are built that way because the engineers picked two-complement before they started designing the thing.

The result is that it happens during the same clock cycle as a non-overflowing result would be returned.

---

How does it work?

The “add 1” stage implements a cascade logic: starting with the LSB each bit is subjected in turn to the truth table

old-bit  carry-in  new-bit  carry-out
-------------------------------------
   0        0        0         0
   0        1        1         0
   1        0        1         0
   1        1        0         1

(that is new-bit = old-bit xor carry-in and carry-out = old-bit and carry-in). The “carry-in” for the LSB is the 1 that we’re adding, and for the rest of the bits it is the “carry-out” of the previous one (which is why this has to be done in a cascade).

The last of these circuits just adds a circuit for signed-overflow = (carry-in and not carry-out).