Question

This is my VERY FIRST Makefile and so I have cut and paste junk I have found all over the web. My directory structure is pretty flat and was not thought out for Makefiles. It is:
Project/
Project/Control
Project/NodeMgmt
Project/Common
Project/Interfaces

I am writing a Makefile for Control and would like it to standalone inside Control. It needs to include compile and include from Common & Interfaces. Here’s my Makefile:

CC = g++

CFLAGS = -Wall -c

INCLUDES = -I/usr/local/include -I/SuperCool/Ion-1.0.0-snapshot-1/include -I/SuperCool/FastrakSDK-4.0.1-snapshot-1/include/Fastrak/Engine/Core/CoreIpc -I/Projects/Common -I/Projects/Interfaces -I/Projects/NodeMgmt -I/Projects/Controller 

LFLAGS = -L/usr/local/lib -L/SuperCool/FastrakSDK-4.0.1-snapshot-1/lib

LIBS = -lCoreIpc4 -lIonOs

VPATH = ../Interfaces/
VPATH = ../Common/
VPATH = ../NodeMgmt/

SRCS = *.cc

OBJS = $(SRCS:.cc=.o)

MAIN = controller

.PHONY: clean

all:    $(MAIN)
    @echo Built Controller

$(MAIN): $(OBJS)
    $(CC) $(CFLAGS) $(INCLUDES) -o $(MAIN) $(OBJS) $(LFLAGS) $(LIBS)

.cc.o:
    $(CC) $(CFLAGS) $(INCLUDES) -c $< -o $@

clean:
    $(RM) *.o $(MAIN)

It’s compiling the first .cc file it finds “-c Controller.cc -o *.o” which make sense but that’s all it’s compiling and I get a *.o output file, not a Controller.o file. It does not compile any other files.

Answer 1

Here’s one problem:

SRCS = *.cc

Make doesn’t understand wildcards without the wildcard function:

SRCS = $(wildcard *.cc)

That should get it working; we can make minor improvements later.