Question

This question is about Altera Quartus. Suppose I have a bdf file with few entities. Each entity has it’s own VHDL file. I found a bug in one of entities and fixed it (edited a vhdl file). What are minimal compilations steps to start a new simulation?

Answer 1

It depends on how clever the compiler is.

If your entity and architecture are in the same file, then in most cases recompiling the architecture will also “touch” the entity, which means that any architecture which instantiates that entity will also need to be recompiled (and so on up).

If you split the entity out into a separate file, then (assuming you only make changes to the architecture) you only have to recompile the file with the architecture in. I used to do this all the time in development to speed the compile/simulate/edit cycle.

(You’re using Qurtus I see, but with Modelsim you can pass a -just a switch to make it only compile architectures and this achieves the same without splitting things out into multiple files. There may be something you can do with Quartus to get it to behave similarly)