Question

Using the following as an example makefile:

CC=g++
CFLAGS=-c -Wall
LDFLAGS=-lfoobar
SOURCES=main.cpp foo.cpp bar.cpp
OBJECTS=$(SOURCES:.cpp=.o)
EXECUTABLE=hello


all: $(OBJECTS) 
    $(CC) $(LDFLAGS) $(OBJECTS) -o $@

$(OBJECTS):
    $(CC) $(CFLAGS) $< -o $@

$< always expands to nothing.

I’ve tried changing it to the following:

CC=g++
CFLAGS=-c -Wall
LDFLAGS=
SOURCES=main.cpp foo.cpp bar.cpp
OBJECTS=$(SOURCES:.cpp=.o)
EXECUTABLE=hello


all: $(OBJECTS)  # or main.o foo.o bar.cpp
    $(CC) $(LDFLAGS) $(OBJECTS) -o $@

.cpp.o:
    $(CC) $(CFLAGS) $< -o $@

This tells me that there’s no rule for main.o

Am I missing something here? I see a lot of make files using these syntaxes and/or variables and dependencies.

Answer 1

Try this:

CXX=g++
CXXFLAGS=-c -Wall
LDFLAGS=
SOURCES=main.cpp foo.cpp bar.cpp
OBJECTS=$(SOURCES:.cpp=.o)
EXECUTABLE=hello

all: $(EXECUTABLE)

$(EXECUTABLE): $(OBJECTS)  # or main.o foo.o bar.cpp
    $(CXX) -o $@ $(LDFLAGS) $(OBJECTS) $(LIBS)

The rule to build each object file is built-in anyway, so there is no need to define it.