Virtual Memory I: the problem [LWN.net]
http://lwn.net/Articles/75174/
in particular, the hardware’s address translation buffer can be shared between the kernel and user space.
I am totally confused about it. Why they can share the TLB when the vm is split? I know there is page global bit in some CPU that
indicating TLB entries are common to different process and need not to be flushed.
What is the relation between TLB and vm split 3G/1G? Please comment in detail. Thanks in advance.
Update:why not use page global bit to indicate the TLB entry is used by OS(kernel space)? If so, why do still need to split the vm space? example: two entry(vm liner address is same) in TLB but one of them the global bit is set. ? When the context switch, just flush the entries that the global bit is not set. Is this possible?
Update2:I checked the intel-ia-32 architectures software developer manual and found that there is no global bit(exists in PDE and PTE) in TLB entry. But when the context switch, how the CPU determine whether TLB entry global bit set or unset?
The TLB also includes a supervisor flag that indicates if the mapping can be used by regular processes or if it is only usable when a process is running with the supervisor flag set — i.e., when the process is executing in kernel context.
This supervisor flag allows the TLB to be useful for both the process (it doesn’t automatically get privileges to the data in the kernel’s gigabyte) and allows the kernel to have complete access to all the process’s memory when executing in kernel mode.
This means a process can enter and exit kernel mode without incurring TLB flush penalties.
If the memory was not split (say, the 4:4 patch giving four gigabytes to userspace and four gigabytes to kernel space is in use) then the TLB must be flushed on every kernel enter / exit to map either the privileged space or the userspace and all data being copied into and out of the kernel must go through tedious remapping mechanisms.