We all know the various ways of testing OO systems. However, it looks like I’ll be going to do a project where I’ll be dealing with PLC ladder logic (don’t ask :/), and I was wondering if there’s a good way of testing the validity of the system.
The only way I see so far is simply constructing a huge table with all known states of the system and which output states that generates. This would do for simple ‘if input A is on, turn output B on’ cases. I don’t think this will work for more complicated constructions though.
The verification of ‘logical’ systems in the IC design arena is known as ‘Design Verification’, which is the process of ensuring that the system you design in hardware (RTL) implements the desired functionality.
Ladder logic can be transformed to one of the modern HDL’s like Verilog.. transform each ladder
to an expression like
or you could use an assign statement
a latching relay
Then use a free verilog simulator like Icarus to develop a testbench and test your system. Make sure you’re testcases give good CODE coverage of your logic! And If your ladder editing software gives you decent naming capabilities, use them, rather than Rnn.
(Note: in Ladder Logic for PLC convention, Rnn is for internal relays, while, Xnn is an input and Ynn is an output, as can be quickly gleaned from one of the online tutorials.
Verilog will be an easier language to develop your tests and testbenches in!
It may be helpful to program in some unit delays.
Sorry, I have never looked for ladder logic to/from verilog translators.. but ladder logic in my day was only just being put into a computer for programming PLC’s – most of the relay systems I used were REAL Relays, wired into the cabinets!!
Good luck. jbd
There are a couple of ladder logic editors (with simultors) available for free.. here is one that runs on windows supposedly:
http://cq.cx/ladder.pl