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Editorial Team
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Asked: 2026-06-02T03:11:48+00:00

We are attempting to write to an SRAM chip on a Terasic DE1 FPGA

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We are attempting to write to an SRAM chip on a Terasic DE1 FPGA board, however we are getting errors to do with tri-state control. The errors are as follows:

Error (10137): Verilog HDL Procedural Assignment error at inputOutputControl.v(32): object "SRAM_DATA" on left-hand side of assignment must have a variable data type
Error (10137): Verilog HDL Procedural Assignment error at inputOutputControl.v(33): object "SRAM_DATA" on left-hand side of assignment must have a variable data type
Error (10219): Verilog HDL Continuous Assignment error at inputOutputControl.v(52): object "SRAM_LB_N" on left-hand side of assignment must have a net type
Error (10219): Verilog HDL Continuous Assignment error at inputOutputControl.v(53): object "SRAM_UB_N" on left-hand side of assignment must have a net type

The module we are having trouble with is shown below, can anybody shed any light on how we can get this working?

module ram_writer(
input               CLK,
input               RESET_N,
input               V_PORCH_EN,
input               LOGIC_WE_N,
input               LOGIC_CE_N,
input        [17:0] LOGIC_WRITE_ADDRESS,        
input        [15:0] LOGIC_WRITE_DATA,
input               VGA_OE_N,
input               VGA_CE_N,
input        [17:0] VGA_READ_ADDRESS,       
output       [15:0] VGA_READ_DATA,
output  reg         SRAM_OE_N,
output  reg         SRAM_WE_N,
output  reg         SRAM_CE_N,
output  reg         SRAM_LB_N,
output  reg         SRAM_UB_N,
output  reg  [17:0] SRAM_ADDRESS,       
inout   wire [15:0] SRAM_DATA   
);

reg [15:0] writeData;

always @(posedge CLK)
begin
   writeData       <= LOGIC_WRITE_DATA;                    
   VGA_READ_DATA   <= SRAM_DATA;
end

always @((posedge LOGIC_WE_N or writeData))
begin
   if( LOGIC_WE_N == 1) SRAM_DATA = 16'bZ;
   else SRAM_DATA = writeData; 
end

always @(posedge CLK)
begin
   if(V_PORCH_EN == 1) begin
   SRAM_ADDRESS <= LOGIC_WRITE_ADDRESS;
   SRAM_CE_N    <= LOGIC_CE_N;
   SRAM_WE_N    <= LOGIC_WE_N; 
   SRAM_OE_N    <= 1;
   end 
   else begin
   SRAM_ADDRESS <= VGA_READ_ADDRESS;
   SRAM_CE_N    <= VGA_CE_N;
   SRAM_OE_N    <= VGA_OE_N; 
   SRAM_WE_N    <= 1;
   end 
end

assign SRAM_LB_N = 0; 
assign SRAM_UB_N = 0; 

endmodule
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1 Answer

  1. Editorial Team

    I think this:

    Error (10137): Verilog HDL Procedural Assignment error at inputOutputControl.v(32): object "SRAM_DATA" on left-hand side of assignment must have a variable data type
Error (10137): Verilog HDL Procedural Assignment error at inputOutputControl.v(33): object "SRAM_DATA" on left-hand side of assignment must have a variable data type

    Refers to this:

    if( LOGIC_WE_N == 1) SRAM_DATA = 16'bZ;
else SRAM_DATA = writeData;

    A ‘wire’ datatype has no memory, so you have to assign it using continuous assignment, not an always block.

    Conversely here:

    assign SRAM_LB_N = 0; 
assign SRAM_UB_N = 0;

    You cannot assign a reg type via continuous assignment, it must be assigned in an always block.

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