Question

what is tail chaining of Interrupts which is supported by NVIC in ARM Cortex M3.

Answer 1

Tail-chaining is back-to-back processing of exceptions without the
overhead of state saving and restoration between interrupts. The
processor skips the pop of eight registers and push of eight registers
when exiting one ISR and entering another because this has no effect
on the stack contents.
Cortex™-M3 Technical Reference Manual

Which basically means, handling pending interrupts without repeating the stacking.

I recommend this book if you want to know more details:

The Definitive Guide to the ARM Cortex-M3