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When CPU uses its program counter to fetch next instruction, does the address of next intruction need to be go to MMU first, so that the address can be turned into physical address, then retrieve the instruction from memory by that physoical address?
All architectures that both have an MMU and share a common address space for instructions and data (including x86) translate their instructions before fetching them. It’s a requirement for it to behave in a sensible way.
However, unlike for data, this rarely causes any performance problems. Code tends to be quite small and localised, so it’s almost certain that translations for all frequently accessed code pages will be cached in the TLB.