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When designing FPGA systems how can I estimate roughly the number of logic blocks a given task would require?
Anyone have a rough order of magnitude on what I should expect for these comon devices?:
I’ve seen http://www.opencores.org, however, they are not giving a number of gates magnitude for each project.
UART: 3200 gates. 8-bit uC: 10k gates. Check http://www.design-reuse.com/ for others.