Question

When we use

input reg [7:0] ast, f_out;

ast === f_out ;

ast <= ast + 8'b00000001;

for those operations ” === and <= “, Have any time delay been occurred ?

EDIT: I think something small like 1 unit time, am I wrong ?

used language : verilog

Answer 1

There will be a simulation cycle delay if you use <= – ie a nonblocking assignment. Read up on blocking vs nonblocking assignments.

Also, === is not an assignment – its an equality operator that doesn’t treat x and z as don’t cares