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Home/ Questions/Q 3335404
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Editorial Team
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Editorial Team
Asked: May 18, 20262026-05-18T00:00:52+00:00 2026-05-18T00:00:52+00:00

consider the following array of bytes that is intended to be converted into a

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consider the following array of bytes that is intended to be converted into a single unsigned integer:

unsigned char arr[3] = {0x23, 0x45, 0x67};

each byte represents the equivalent byte in integer, now which one of the following methods would you suggest specially performance-wise:

unsigned int val1 = arr[2] << 16 | arr[1] << 8 | arr[0];
//or
unsigned int val2=arr[0];
*((char *)&val2+1)=arr[1];
*((char *)&val2+2)=arr[2];
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  1. Editorial Team
    Editorial Team
    2026-05-18T00:00:53+00:00Added an answer on May 18, 2026 at 12:00 am

    This depends on your specific processor, a lot.

    For example, on the PowerPC, the second form — writing through the character pointers — runs into a tricky implementation detail called a load-hit-store. This is a CPU stall that occurs when you store to a location in memory, then read it back again before the store has completed. The load op cannot complete until the store has finished (most PPCs do not have memory store-forwarding), and the store may take many cycles to make it from the CPU out to the memory cache.

    Because of the way the store and arithmetic units are arranged in the pipeline, the CPU will have to flush the pipeline completely until the store completes: this can be a stall of twenty cycles or more during which the CPU has stopped dead. In general, writing to memory and then reading it back immediately is very bad on this platform. So on this case, the sequential bitshifts will be much faster, as they all occur on registers, and will not incur a pipeline stall.

    On the Pentium series, the situation may be entirely reversed, because that chipset does have store forwarding and a fast stack architecture, and relatively few architectural registers. On the Core Duos and i7s, it may reverse yet again, because their pipelines are very deep.

    Remember: it is not the case that every opcode takes one cycle. CPUs are not simple, and things like superscalar pipes and data hazards may cause instructions to take many cycles, or even many instructions to occur per cycle, depending on just how you arrange your code.

    All of this just to underscore the point: this sort of optimization is extremely specific to a particular compiler and chipset. So you must compile, test and measure.

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