Question

First off, I would like to state this is on a practice exam I am taking. I know the answers to be: cout = 4ns, and S = 7ns. Just looking for a little explanation. Thanks in advance.

For the VHDL implementation of a full adder shown below, when do the outputs cout and S settle at their final values (consider the worst case timing path with the worst case inputs)?

         architecture concurrent_behavior of full_adder is
            signal t1, t2, t3, t4, t5: std_logic;

         begin
             t1 <= not A after 1 ns;
             t2 <= not cin after 1 ns;
             t4 <= not ((A or cin) and B) after 2 ns;
             t3 <= not ((t1 or t2) and (A or cin)) after 2 ns;
             t5 <= t3 nand B after 2 ns;
             S <= not((B or t3) and t5) after 2 ns;
             cout <= not(t1 or t2) and t4) after 2 ns;
         end concurrent_behavior;

Answer 1

You basically just trace through the dependencies, and add up the dependencies for each route through the logic. Normally it’s easiest to trace backwards from an output to the inputs it needs. For example:

cout <= not(t1 or t2) and t4) after 2 ns;

So, the last stage for cout has a 2 ns delay. Its inputs are t1, t2 and t4, so its 2 ns delay can’t start until t1, t2 and t4 are all ready (i.e., the single longest of those delays determines the start time for the last stage).

In this case, t1 and t2 are delayed by 1 ns apiece, and t4 is delayed by 2 ns. Therefore, the last stage starts 2 ns after the initial input. That gives 2+2 = 4 ns from initial input to final output.

Looking at it from an algorithmic viewpoint, we could state it that the delay for any signal is the delay of the final “stage” for that signal plus the maximum of the delays for any of its inputs.

For S:

total = 2 + max_delay(B, t3, t5)
total = 2 + delay(t5);
total = 2 + 2 + max_delay(t3, B)
total = 2 + 2 + delay(t3)
total = 2 + 2 + 2 + max_delay(t1, t2, A, cin)
total = 2 + 2 + 2 + delay(t1) (or delay(t2) -- they're the same).
total = 2 + 2 + 2 + 1