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Home/ Questions/Q 9116185
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Editorial Team
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Editorial Team
Asked: June 17, 20262026-06-17T04:36:42+00:00 2026-06-17T04:36:42+00:00

For simplifying discussion, I assume there is only one executing thread. The following are

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For simplifying discussion, I assume there is only one executing thread. The following are just my wild speculations:

1, If the CPU reads a byte from an address of memory, then it can repeatedly read the same value from the same address.

2, If the CPU reads a byte from a port repeatedly, then it may read a different value each time.

I think the difference between the two ways is that the port controller can automatically update the value on the port after each read operation.

However, I could not find any text book explicitly supporting my statements.

Am I correct?

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  1. Editorial Team
    Editorial Team
    2026-06-17T04:36:43+00:00Added an answer on June 17, 2026 at 4:36 am

    IO instructions are supposed to interact with hardware. Therefore IO instructions in general do not (and are not supposed to) conform to memory semantics. Instead, the semantics depends on the hardware (and the corresponding protocol) they communicate with. Don’t think of the IO space as memory.

    Memory instructions can access memory as well as memory mapped IO. When they access memory mapped IO they behave like IO instructions. Only when they do access real memory, memory semantics apply. This means for example that a read to a memory location always returns the last value that was written to this location.

    It is important for the CPU to distinguish between address spaces used for memory mapped IO and for real memory. For example data from memory mapped IO must not be stored in the cache and memory instructions must not speculatively access memory mapped IO locations. Because of this accessing a memory mapped IO space is significantly slower than accessing real memory.

    To distinguish between memory mapped IO and real memory the processor usually uses the page table, but there are other mechanisms like Memory type range registers.

    Last not least there may be other hardware able to write to memory. Examples are systems with multiple cores and/or direct memory access. These systems need to be aware of each other and use a cache coherency protocol to maintain the correct memory semantics. Of curse this also requires to distinguish between IO mapped memory and real memory.

    The conclusion is that real memory also behaves like memory and conforms to memory semantics. IO and memory mapped IO can behave any way it wants.

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