Question

I have a make file that uses pattern matching to automate compilation using a rule like this:

%.o : %.c
    gcc -c $<

However in this project I have a number of source files which differ in case of their extension. Is there a way to match sets in make files like in regular expressions.

Pseudo-example:

%.o : %.[cC]
    gcc -c $<

It is not possible to simply change the case of the source files as this is used for module testing of an existing project which mixes modules from several other.

Answer 1

I found the solution. It turns out that the makefile had several issues.

First the example I posted actually works as Banthar pointed out. However my problem was that my sourcefiles weren’t in the root directory but in a src/ subdirectory which I had added to vpath. I honestly thought it was irrelevant to my question as I believed make would automatically scan its vpath for source files. Turns out vpath does not apply to rule checking.

To make it work do:

vpath = %.c src
vpath = %.C src

%o : src/%.[Cc]
    gcc -c $<

Next as I was working through examples of how to get it done make would sometimes build sourcefiles behind my back. If you do:

all : main.o
    gcc -o test main.o

… and not have rule to build the .o file make will build it using implicit inbuild rules. Quite confusing. It can be disabled using the -r flag.

make -r all

Third compiling .C files using gcc without any extra options will result in linker errors because gcc interprets .C files as C++ files as default. In order to compiles as C files use -x flag.

%.o : %.C
    gcc -x c -c %<

Hope this helps someone.