Question

I have a signal in VHDL declared like this :

signal Temp_Key : std_logic_vector(79 downto 0);

This Temp_Key is passed through a for loop 31 times and it is modified. I want to store all the 31 different Temp_Keys in an array.

Is it possible to use multi-dimensional arrays in VHDL to store 80 bit signals ?

Answer 1

Yes, first you need to declare a type:

type YOUR_ARRAY_TYPE is array (0 to 30) of std_logic_vector(79 downto 0);

Note you can also declare the type to be of undefined length – so you can specify how many 80 bit words it has when you declare your signal. And with VHDL 2008, you can also leave the size of the slv unspecified, also to be declared when you create your signal. For example:

type slv_array is array (natural range <>) of std_logic_vector;

and then use it

signal MY_SIGNAL : YOUR_ARRAY_TYPE;
...
MY_SIGNAL(0) <= data;
...
MY_SIGNAL(1) <= data;

See here for a reference.