Question

I have several .cpp and .hpp files. I want compile and lnk them over using make. How can I do that ?

    sample.cpp sample.hpp
    sample_2.cpp sample_2.hpp
    sample_3.cpp sample_3.hpp
    ...
    and 
    main.cpp

    I have done :

    default:

             g++ -c sample sample.cpp
             g++ -c sample_2 sample_2.cpp
             g++ -c sample_3 sample_3.cpp

             g++ -o main main.cpp sample sample_2 sample_3

When I type make on terminal, it gives error :

 /usr/bin/ld: /usr/lib/debug/usr/lib/x86_64-linux-gnu/crt1.o(.debug_info): relocation 0 has invalid symbol index 10

Answer 1

Instead of having a single default target that does everything each separate output should be a make target. That allows make to work properly, building one thing at a time, in the correct order (or in parallel if the dependency graph allows it) and reporting errors properly at each step. Also, very importantly, by telling make about each separate target and what they depend on you ensure that when a dependency changes make will know exactly what targets need to be rebuilt because of the changed dependency. That is Make’s best feature.

In your case the final target is main so you want the default target to build that, which you do by saying main is a prerequisite of main:

default: main

Now you need to say how to build main, it depends on the various object files, so we tell make that:

main: main.o sample.o sample_2.o sample_3.o

This says it depends on those object files (they are its prerequsites) and so they’ll be built first. Each of those objects is another make target that will be built separately.

When all the prerequisites have been built a recipe will be used to link them into main, so we need to add a recipe to the above target:

main: main.o sample.o sample_2.o sample_3.o
        g++ main.o sample.o sample_2.o sample_3.o -o main

Make has lots of abbreviations to simplify things, e.g. $(CXX) is the C++ compiler, $@ means the current target and $^ means the current target’s prerequisites, so you can simplify that rule to:

main: main.o sample.o sample_2.o sample_3.o
        $(CXX) $^ -o $@

That’s actually all you need, Make already knows how to build the .o prerequisites using its builtin rules, so it will see a file called main.cpp and know it can compile that to create main.o, and see sample.cpp and compile that to sample.o etc. It will create a dependency graph from the makefile to decide what targets are needed in order to build default (which means it decides it needs main and that needs main.o, sample.o etc. and they need main.cpp and sample.cpp etc. which already exist, so it can start building prerequisites until it has everything needed to link main then it can do that and finish.)

Now if you alter sample_2.cpp and run make again it will see that sample_2.o is out of date and needs to be recompiled, but the other .o files are still OK (they are newer then the .cpp files they depend on), so it will recompile sample_2.o and relink main and not rebuild everything else.

In fact you could simplify it even further, by using the default recipe for linking objects into an executable:

LINK.o = $(CXX)

default: main

main: main.o sample.o sample_2.o sample_3.o

That’s all you need! But it’s often clearer, especially for a beginner, to go with the more verbose version, as it’s easier to customise when you’re not familiar with all of Make’s automatic rules and variables.

It’s also helpful to tell make about dependencies on header files, so that things get rebuild when headers change. That can be done automatically using the compiler to generate prerequisites, but for simple cases you can just add it to the makefile directly e.g.

sample.o: sample.hpp sample.cpp