Question

I have the following Makefile rules:

DIR = src
SOURCES = $(shell find $(DIR) -name "*.cpp")
OBJS := $(SOURCES:.cpp=.o)

With this definition all my .o files are located in the same directories (and sub-directories) as their .cpp counterparts. Such allocation principle turns the project directory into a mess very soon (with 50+ files). I would like to make a new specific folder for .o files and place them there. I need to write a make-rule that will convert every .o file name like the following:

foo/bar/test.o —> objects/foo-bar-test.o

How can I create such a rule in Makefile? Thanks in advance!

Answer 1

I’m not sure if you can specify patterns with these modification directly, but you always can use macros (at least in GNU make). An example could be this:

define export_rule
objects/$(patsubst %.cpp,%.o,$(subst /,-,$(1))) : $(1)
    <<your rules here>>
endef


SOURCES = $(shell find $(DIR) -name "*.cpp")

$(foreach s,$(SOURCES), $(eval $(call export_rule,$(s))))

This defines the exact rules you want, avoiding (as some solutions proposed above) the name clashes in case two files with the same name reside in different directories.