Question

I have this SV code :

module m1 (input int a);
    always begin #1; force a=a+1; end
endmodule

module m ();
    int a;  
    m1 m1(a);
endmodule

Is this statement in above code valid force a=a+1;?

Answer 1

It might work in your simulator, however it is not recommended.

In the IEEE std 1800-2009 section 10.6 defines a force statement as a “procedural continuous assignment.” There is an example in the LRM stating that if a value on the right hand side of the equation is changes, then it will force the new value to the right hand variable. In this case a=a+1 should technically cause an infinite loop but likely does not because of a scheduling rule.

In general force should be used sparingly and be used in a test bench and behavioral modeling. Functional expressions are allowed with force however circular dependance needs to be avoided. Best to assign a constant expression with force is possible.