Sign Up to our social questions and Answers Engine to ask questions, answer people’s questions, and connect with other people.
Login to our social questions & Answers Engine to ask questions answer people’s questions & connect with other people.
Lost your password? Please enter your email address. You will receive a link and will create a new password via email.
Please briefly explain why you feel this question should be reported.
Please briefly explain why you feel this answer should be reported.
Please briefly explain why you feel this user should be reported.
In a verilog simulation, I will have to communicate with the 64K I2C EEPROM from Microchip. Every time for getting an ack from slave, I am driving my SDA to high impedance for a given clock period. Now, in order to get data from slave, should I have to follow the same for SDA? Simply, should the SDA ports have to be driven to high impedance state ?
In a physical I2C circuit, there are pull-up resistors that make SCL and SDA go high when their outputs are in their high impedance states. The Verilog equivalent to the pullup resistor is the TRI1. This will make the lines defined rather than floating when the signals are in their high impedance state.