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In designing a circuit in verilog using top-down method, I can start from the behavior of a circuit followed by defining the details in every module to construct a structural circuit that is synthesizable.
But how can I know if my code is synthesizable?
Are there any guidelines to follow to support synthesis in verilog?
There is a ‘standard’, IEEE 1364.1 but as Martin pointed out each tool supports whatever it wants. I recommend the Xilinx XST User Guide if you need a free resource.
Also, structural verilog typically means you are creating description close to a netlist and the constructs you would use in this case are a small subset of those that are synthesizable.