May be this question a bit not for StackOverflow, but both compilers and Verilog (which can be considered as programming language) are related to this project.
Where can I find a open-source (or downloadable and free-to-noncommercial-use) compiler from Verilog language to the GDSII format or to Netlist? There are a lot of Verilog simulators (which compile it to native machine code or to the C), a lot of Verilog-to-FPGA compilers, but I want compiler, able to generate geometric structures of transisors from Verilog.
Netlist is http://en.wikipedia.org/wiki/Netlist – interconnect of IC elements, such as transistor, resistor or even cells (?). It can be converted to GDSII, but if compiler works on “Verilog->Netlist”, I also need a free convertor “Netlist->GDS2”.
GDSII http://en.wikipedia.org/wiki/GDSII – is a format of VLSI integrated circuits (IC), which is acceptable by founrdies for IC fabrication. It is nearly impossible to a single human to get his GDSII fabricated in Silicon, but I think, it can be intresting to try of compiling small examples.
This compiler can use “full-custom” (it will draw all transistors itself), or “cell-based” designs (verilog is compiled into a geometric set of some library cells).
Of course, the compiler required can be a university project, which can’t compile a big verilog project.
Thanks.
Usually the steps are:
Verilog -> [Compiler] -> Gate-level netlist -> [Place & Route tool] -> GDSII
You’d need an open-source cell library too. Do a quick interweb search for that, and a place & route tool may show up.