Question

Reading some Verilog code, there seem to be two ways of defining arguments in function declaration:

Method 1:

function factorial;
    input [3:0] operand;
    // More code
endfunction

Method 2:

function factorial(input [3:0] operand);
    // More code
endfunction

Is there any difference between the two? Are both methods equally portable?

Answer 1

I believe they are equivalent.

From a manual the definition of a function:

function [automatic] [signed] [RangeOrType] functionName [(FunctionPorts)];
 Declarations ...
 begin
  ...code...
 end
endfunction

FunctioPort
 input [reg]  [signed] [Range] names
 input [Type] names

Declaration
 input [reg]  [signed] [Range] names
 input [Type] names
 Variable
 Parameter
 Event