Question

This is a simple SystemVerilog question that I am having a surprisingly difficult time finding the answer for.

In this kind of bit array initialization syntax, is the b[0] part assigned to a’s most significant bit, or the least significant bit?

bit a[7:0];
bit b[7:0] = 8'hff;
bit c[7:0] = 8'h00;

a = {b[0], c[6:0]};

So does a[0] == 1 or a[7] == 1?

Answer 1

The reason you’ve found it hard to find an answer is because the result is dependent on how you’ve declared things.

You’ve declared a to be [7:0]. Therefore the bits in a are arranged like this:

a7 a6 a5 a4 a3 a2 a1 a0

You then assign {b[0], c[6:0} to a:

a7 a6 a5 a4 a3 a2 a1 a0 = b0 c6 c5 c4 c3 c2 c1 c0
 1  0  0  0  0  0  0  0 =  1  0  0  0  0  0  0  0

A[7] == 1

If you’d declared a to be [0:7] the result would have been:

a0 a1 a2 a3 a4 a5 a6 a7 = b0 c6 c5 c4 c3 c2 c1 c0
 1  0  0  0  0  0  0  0 =  1  0  0  0  0  0  0  0

A[0] == 1