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Asked: 2026-05-19T23:42:06+00:00

LIBRARY ieee; USE ieee.std_logic_1164.all; USE ieee.std_logic_1164_unsigned.all; ENTITY alu IS PORT (a: IN STD_LOGIC_VECTOR (15

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LIBRARY ieee;
USE ieee.std_logic_1164.all;
USE ieee.std_logic_1164_unsigned.all;

ENTITY alu IS
    PORT (a: IN STD_LOGIC_VECTOR (15 DOWNTO 0);
          b: IN STD_LOGIC_VECTOR (15 DOWNTO 0);
          operation: IN INTEGER (1 TO 10);
          result: OUT STD_LOGIC_VECTOR (15 DOWNTO 0);
    );

ARCHITECTURE arch-alu OF alu IS
    SIGNAL arith, logic: STD_LOGIC_VECTOR (15 DOWNTO 0);
    BEGIN
----rest of the code which give values to arith and logic----
    WITH operation SELECT
        result <= arith WHEN (1 TO 5),
                  logic WHEN (6 TO 10);
END arch-alu

My query is: Can I put a range after WHEN (as in the code), or I have to specify one by one each possibility of the signal.

Thanks!

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1 Answer

  1. Editorial Team

    According to http://tams-www.informatik.uni-hamburg.de/vhdl/tools/grammar/vhdl93-bnf.html the syntax you’ve used is permitted by VHDL ’93 (the productions to look at there, in order: selected_signal_assignment, selected_waveforms, choices, choice, discrete_range, range) except that the grammar there doesn’t seem to allow for the parentheses around the ranges. See also http://www.vhdl.renerta.com/source/vhd00063.htm (which again has no parens around the ranges).

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